Certain digital circuits employ a first-in first-out (FIFO) synchronizer to decouple transmitter from receiver timing. For example, certain dynamic random access memory (DRAM) devices use a FIFO synchronizer to transfer command/address signals timed to a command capture clock to the timing domain of an array/core logic clock. An example of a FIFO synchronizer circuit is described by William J. Dally and John W. Poulton in “Digital Systems Engineering”, Cambridge University Press, Cambridge, U.K. 1998.
One impact of a FIFO synchronizer is that there is a latency associated with the transfer of the command/address signals from the sending clock domain to the receiving clock domain. The length of this transfer latency is dependent upon the clock frequency, and the timing relationship between the two clock signals. The frequency of the sending clock signal is typically the same as that of the receiving clock signal. However, there is no predetermined phase relationship between the sending and the receiving clock signals.
In digital circuits that employ a FIFO synchronizer to transfer command/address signals between clock domains, these command/address signals are transferred directly, with only the timing of these signals being modified. Thus, the latency that is associated with the transfer of these signals is not employed for any useful purpose. In other words, the transfer latency represents wasted time. Thus, it would be advantageous to provide an apparatus and a method for transferring signals between timing domains that makes the latency associated with performing the transfer available for performing a useful purpose.